The subject matter of this invention relates to methods of fabricating semiconductor devices. More particularly, the subject matter of this invention relates to methods of making inductors with reduced parasitic capacitance.
System-on-chip solutions need an increasing amount of on-chip high inductance and high quality factor inductors. Inductors are designed to minimize series resistance, and maximize inductance, with low parasitic components. FIG. 1 is a schematic illustration of an exemplary inductor having parasitic capacitances Cox and Cint in a system on chip, wherein Cox is the capacitance between the substrate 110 and the inductor loops 122 and Cint is the capacitance between the inductor loops 122. The parasitic capacitances, Cint, Cox as shown in FIG. 1, driven by the dielectric present around the inductor coils degrade the inductor performance.
A conventional solution to improving inductor performance is a poor-gap-fill solution. This approach uses ALCAP (aluminum capping) level inductors with appropriately chosen spacing and dielectric gap fill properties. Even though the utilization of ALCAP level for inductors is unique, this approach has a major drawback as aluminum is not the preferred material for inductor coils. Another conventional solution utilizes wet etching dielectric in the inductor area followed by a poor-gap-fill dielectric deposition. However, this method is costlier and the wet etching of the dielectric poses a potential negative impact to the integrity of Cu metallization.
Thus, there is a need to overcome these and other problems of the prior art and to provide methods of reducing parasitic capacitance in the inductors.